Rodrigo Liang is the co-founder and CEO of SambaNova Systems, which builds a vertically integrated AI-computing stack around its Reconfigurable Dataflow Unit. The company’s current position is materially different from the sale narrative circulated in late 2025: SambaNova and Intel announced a multi-year collaboration in February 2026, and SambaNova announced the first close of a $1 billion financing at an $11 billion post-money valuation in July.

As of September 13, 2026, no source reviewed here shows that Intel acquired SambaNova. The available evidence instead shows financing, an Intel investment, and a product collaboration. The distinction turns a purported collapse story into a still-unproven execution story: SambaNova has capital and a differentiated architecture, but buyers still need workload-level evidence.

Career and founding record

SambaNova’s current leadership page identifies Liang as co-founder and CEO and says he previously led processor teams at Sun Microsystems and Oracle. A U.S. government PCAST speaker biography offers external corroboration: it describes him as a former Oracle senior vice president responsible for SPARC processor and ASIC development and a former Sun vice president, with electrical-engineering degrees from Stanford.

SambaNova was founded in 2017 by Liang, Stanford professor Kunle Olukotun, and Stanford professor Christopher Re. The combination is relevant because an accelerator company has to solve more than chip design. It needs a compiler, runtime, memory system, packaging, networking, model support, and a commercial delivery model.

Liang’s background supports the claim that he had experience managing complex processor programs. It does not show that he personally invented every element of the RDU. SambaNova’s papers list large engineering teams, and the architecture draws on research and implementation across the company and its academic roots.

How the dataflow architecture differs

Conventional processors fetch and schedule instructions while moving data through a memory hierarchy. SambaNova’s approach compiles a model into a spatial dataflow graph so that operations and movement can be mapped across reconfigurable hardware. The company argues that co-designing compiler, software, memory, and silicon improves utilization for AI workloads.

A SambaNova-authored SN40L paper describes a three-tier memory system, an inter-RDU network, and experiments with a composition-of-experts workload. It reports speedups against specified Nvidia DGX systems. The paper provides architecture and methodology detail, which is better evidence than a marketing slogan. It remains author-affiliated research and tests selected configurations.

A second SambaNova-authored paper on kernel looping explains an optimization intended to reduce synchronization overhead during token generation. Again, the results are bounded by the models, batch settings, hardware counts, software versions, and baselines used in the study.

Independent work is beginning to make cross-architecture measurement more systematic. The DABench-LLM paper proposes a framework and reports tests across SambaNova RDU, Cerebras WSE-2, and Graphcore IPU. That paper does not certify any system as universally superior. It supports the need to examine allocation, bottlenecks, and scaling rather than rely on one token-per-second figure.

The Intel relationship replaced the acquisition story

Intel announced on February 24, 2026 that it and SambaNova planned a multi-year strategic collaboration. Intel said Intel Capital would participate in SambaNova’s financing and framed the work as heterogeneous infrastructure built around Xeon hosts and SambaNova inference technology.

On April 8, Intel described a joint rack-scale blueprint combining CPUs, GPUs, networking, and RDUs for different phases of inference. The announcement projected availability in the second half of 2026. A projection is not a shipment record, so customers should verify current production status, configurations, and support.

These primary announcements do not describe an acquisition. They also do not disclose every commercial term, intellectual-property right, supply commitment, or customer obligation. The appropriate conclusion is that two companies chose a joint architecture and investment relationship after reported deal talks did not produce a disclosed sale.

Financing claims and their limits

SambaNova announced on July 8, 2026 that it had completed the first close of $1 billion in Series F financing at an $11 billion post-money valuation. The release names General Atlantic as lead investor and lists Intel Capital and other participants. It also describes a JPMorganChase selection of RDUs.

These are company disclosures. “First close” means the round may have additional closings; it should not be silently converted into a final-round total. A private post-money valuation records financing terms, not a continuously observable market value. The release does not provide audited revenue, margins, cash use, order backlog, or the commercial scope of the cited customer relationship.

TechCrunch’s report on the round supplies named reporting and context about prior Intel talks. It does not change the evidence boundary around private finances. The current valuation also should not be back-projected to claim that earlier reported valuations “cratered” or recovered without matching transaction definitions.

Why “Nvidia challenger” is an incomplete category

Nvidia offers chips, networking, systems, software libraries, developer tools, and cloud availability. Competing with that platform is not the same as producing a benchmark in which one accelerator is faster. A customer may prefer a specialized system for a stable inference workload while retaining GPUs for training, broad model compatibility, or rapidly changing code.

SambaNova and Intel now describe a heterogeneous design rather than a single architecture replacing every GPU. That is a more testable proposition. Prefill, decoding, host work, networking, retrieval, and agent tools have different compute and memory characteristics. The best system may assign them to different components.

The cost is operational complexity. A heterogeneous rack introduces compilers, runtimes, observability, scheduling, capacity planning, failure handling, and support boundaries across vendors. Any performance benefit must exceed the integration and switching costs.

A buyer’s benchmark protocol

Before comparing hardware, freeze the model revision, precision, context distribution, output lengths, sampling, concurrency, service-level objective, and accuracy threshold. Report software and compiler versions along with the physical configuration.

Measure:

  • time to first token at median and tail latency;
  • inter-token latency and total request time;
  • throughput at realistic concurrency;
  • accuracy or quality after quantization and optimization;
  • performance per rack, watt, and dollar;
  • model compilation and switching time;
  • availability, recovery, and degraded-mode behavior; and
  • engineering time required to port and operate the workload.

Published peak speed is not enough. Sustained production tests should include variable prompts, bursts, long contexts, retrieval, safety filters, and networking. Power figures should include the system boundary being compared, not only the accelerator.

For an agent workload, separate inference from external actions. A fast decoder cannot fix slow APIs, tool failures, or repeated planning loops. Measure the cost and latency of accepted completed tasks, not tokens alone.

What the record supports

Liang has a documented processor-engineering career and remains SambaNova’s CEO. The company has published technical work on its RDU stack, established a formal Intel collaboration, and announced substantial 2026 financing. These facts make SambaNova a credible alternative architecture to evaluate.

Public evidence does not show that an Intel acquisition occurred, that SambaNova’s system universally beats Nvidia, or that the announced valuation translates into revenue or profitability. Product speed and total cost remain sensitive to workload and configuration. Vendor papers need reproduction or customer-specific testing.

The durable assessment is not whether Liang “defeated” a dominant chip company. It is whether SambaNova can convert a differentiated compiler-and-hardware design into repeatable deployments with competitive economics, model coverage, reliability, and support.

Source and correction note

This revision uses a U.S. government biography, current SambaNova and Intel announcements, technical papers, an independent benchmarking paper, and named reporting available through September 13, 2026. Company benchmarks and financing figures are attributed. The previous version treated anonymous acquisition discussions and an implied valuation decline as established events, narrated private management decisions, and framed the architecture as destined to make GPUs obsolete. Those claims have been removed and the 2026 collaboration and financing added.